Webinar on high-level synthesis (HLS) for high-performance digitizers

Date:


Webinar on high-level synthesis (HLS) for high-performance digitizers

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Be taught the fundamentals of how HLS helps simplify FPGA firmware growth for high-performance digitizers

Date: Tuesday, September 27, 2022

Time: 10 AM PDT | 1 PM EDT

Period: half-hour

Learn about digitizer basics

Be part of Teledyne SP Gadgets for an introductory webinar on HLS within the context of high-performance digitizers.

Subjects coated on this webinar:

  • Advantages of onboard FPGA sign processing
  • FPGA structure and growth fundamentals
  • Programming languages and growth instruments
  • Software areas and sign processing examples

Who ought to attend? Builders that need to study extra concerning the potentialities and advantages of onboard digital sign processing in high-performance digitizers.

What attendees will study? An introduction to FPGA growth for high-performance digitizers.

Presenter: Thomas Elter, Senior Subject Functions Engineer

Register beneath to attend the webinar

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